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| MITSUBISHI M62393P/FP 8-BIT 8CH I 2 C-BUS D-A CONVERTER WITH BUFFER AMPLIFIERS DESCRIPTION The M62393 is an integrated circuit semiconductor of CMOS structure with 8 channels of built-in D-A converters with output buffer operational amplifiers. The input is 2-wires serial method is used for the transfer format of digital data to allow connection with a microcomputer with minimum wiring. The output buffer operational amplifier employs AB class output circuit with sync and source drive capacity of 1.0mA or more,and it operates in the whole voltage range from VrefU to ground. And because of connects maximum 8 pieces to 64 channels control. PIN CONFIGURATION (TOP VIEW) R SCL SDA Ao5 Ao6 Ao7 Ao8 VrefL VrefU1 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 CS0 CS1 CS2 VDD Vcc Ao4 Ao3 Ao2 Ao1 VrefU2 FEATURES *Digital data transfer format I 2C-bus serial data method *Output buffer operational amplifier it operates in the whole voltage range from VrefU(0 to 5V)to ground. *High output current drive capacity 1.0mA over *Preparation two high level reference voltage terminal because there are two high level reference voltage terminal,it can set up two kinds differ voltage range. Outline 20P4(P) 20P2N-A(FP) APPLICATION Conversion from digital control data to analog control data for home-use and industrial equipment. Signal gain control or automatic adjustment of DISPLAYMONITOR or CTV. BLOCK DIAGRAM CS0 CS1 CS2 VDD 20 19 18 17 Ao4 15 Ao3 14 Ao2 13 Ao1 12 Vcc VrefU2 16 11 CHIP SELECT 8bit upper segment R-2R 8bit Latch 8bit upper segment R-2R 8bit Latch 8bit upper segment R-2R 8bit Latch 8bit upper segment R-2R 8bit Latch 8 8bit Latch 8bit upper segment R-2R 8bit Latch 8bit upper segment R-2R 8bit Latch 8bit upper segment R-2R 8bit Latch 8bit upper segment R-2R 1 2 3 8 4 5 6 7 10 9 R SCL SDA VrefL Ao5 Ao6 Ao7 Ao8 GND VrefU1 MITSUBISHI ELECTRIC ( 1/5) MITSUBISHI M62393P/FP 8-BIT 8CH I 2 C-BUS D-A CONVERTER WITH BUFFER AMPLIFIERS EXPLANATION OF TERMINALS Pin No. 3 1 2 12 13 14 15 4 5 6 7 16 17 10 8 9 11 18 19 20 Symbol SDA R SCL Ao1 Ao2 Ao3 Ao4 Ao5 Ao6 Ao7 Ao8 VCC VDD GND VrefL VrefU1 VrefU2 CS2 CS1 CS0 8-bit D-A converter output terminal Function Serial data input terminal Reset signal input terminal Serial clock input terminal Analog power supply terminal Digital power supply terminal Analog and digital common GND D-A converter low level reference voltage input terminal D-A converter high level reference voltage input terminal 1 D-A converter high level reference voltage input terminal 2 Chip select data input terminal 2 Chip select data input terminal 1 Chip select data input terminal 0 MITSUBISHI ELECTRIC ( 2/5) MITSUBISHI M62393P/FP 8-BIT 8CH I 2 C-BUS D-A CONVERTER WITH BUFFER AMPLIFIERS ABSOLUTE MAXIMUM RATINGS Symbol VCC VDD VrefU1,2 VIN Vo Pd Topr Tstg Parameter Supply voltage Supply voltage D-A converter high level reference voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature Conditions Ratings -0.3 to +7.0 -0.3 to +7.0 -0.3 to +7.0 -0.3 to VDD+0.3 -0.3 to VDD+0.3 990(DIP)/590(FP) -20 to +85 -55 to +125 Unit V V V V V mW C C ELECTRICAL CHARACTERISTICS Digital part(Vcc,VDD,VrefU1,2=+5V10%,VccVrefU1,2,GND=VrefL=0V,Ta=-20 to +85C,unless otherwise noted) Symbol VDD IDD IILK VIL VIH Parameter Supply voltage Supply current Input leak current Input low voltage Input high voltage CLK=1MHz operation IAO=0A VIN=0 to Vcc -10 0.8VCC 10 0.2VCC Test conditions Min. 4.5 Limits Typ. 5.0 Max. 5.5 Unit V mA A V V Analog part(Vcc,VDD,VrefU1,2=+5V10%,VccVrefU1,2,GND=VrefL=0V,Ta=-20 to +85C,unless otherwise noted) Symbol Vcc Icc IrefU VrefU VrefL VAO IAO SDL SL SZERO SFULL Co Ro Parameter Supply voltage Supply current D-A converter high level reference voltage input current D-A converter high level reference voltage range D-A converter low level reference voltage range Buffer amplifier output voltage range Buffer amplifier output current range Differential nonlinearity Nonlinearity Zero code error Full scale error Output capacitative load Buffer amplifier output impedance CLK=1MHz operation IAO=0A VrefU=5V VrefL=0V Data condition:at maximum current The output does not necessarily be the values within the reference voltage setting range. IAO=100A IAO=500A Upper side saturation voltage=0.3V Lower side saturation voltage=0.2V VrefU=4.79V VrefL=0.95V Vcc=5.5V(15mV/LSB) without load(IAO=0) 3.5 GND 0.1 0.2 -1.0 -1.0 -1.5 -2.0 -2.0 5.0 Vcc Vcc-3.5 Vcc-0.1 Vcc-0.2 1.0 1.0 1.5 2.0 2.0 0.1 Test conditions Min. 4.5 Limits Typ. 5.0 Max. 5.5 Unit V mA mA V V V mA LSB LSB LSB LSB F MITSUBISHI ELECTRIC ( 3/5) MITSUBISHI M62393P/FP 8-BIT 8CH I 2 C-BUS D-A CONVERTER WITH BUFFER AMPLIFIERS I 2 C-BUS LINE CHARACTERISTICS Symbol fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO SCL clock frequency Time the bus must be free before a new transmission can start Hold time start condition.After this period.The first clock pulse is generated The low period of the clock The high period of the clock Set up time for start condition(only relevant for a repeated start condition) Hold time data Set up time data Rise time of both SDA and SCL lines Fall time of both SDA and SCL lines Set up time for stop condition 4.0 Parameter Normal mode Max Min 0 100 4.7 4.0 4.7 4.0 4.7 0 250 1000 300 High speed mode Max Min 0 400 1.3 0.6 1.3 0.6 4.7 0 100 20 20 0.6 0.9 300 300 Unit kHz s s s s s s ns ns ns s *Note that transmitter must internally at reset a hold time to bridge the undefined region(max.300ns)of the falling edge of SCL. TIMING CHART tR, tF tBUF VIH SDA VIL tHD:STA VIH SCL tSU:DAT tHD:DAT tSU:STA tSU:STO VIL tLOW S tHIGH S P S MITSUBISHI ELECTRIC ( 4/5) MITSUBISHI M62393P/FP 8-BIT 8CH I 2 C-BUS D-A CONVERTER WITH BUFFER AMPLIFIERS I2C BUS FORMAT STA SLAVE ADDRESS W A SUB ADDRESS A DAC DATA A STP DIGITAL DATA FORMAT *SLAVE ADDRESS FIRST 1 0 0 1 A2 A1 *SUB ADDRESS FIRST X X X X S3 S2 S1 LAST A0 LAST S0 (SLAVE ADDRESS) CHIP SELECT DATA DON'T CARE CHANNEL SELECT DATA *DAC DATA FIRST MSB D7 D6 D5 D4 D3 D2 D1 LAST LSB D0 (1)CHIP SELECT DATA MSB LSB A2 0 0 0 A1 0 0 1 A0 0 1 0 CS2 0 0 0 CS1 0 0 1 CS0 0 1 0 (2)CHANNEL SELECT DATA MSB LSB S3 0 0 0 S2 0 0 0 S1 0 0 1 S0 0 1 0 Channel selection Don't care. ch1 selection ch2 selection 0 1 1 1 1 1 1 1 1 1 0 0 1 0 0 1 0 1 ch11 selection ch12 selection Don't care. 1 (3)DAC DATA FIRST MSB D7 0 0 0 0 D6 0 0 0 0 D5 0 0 0 0 D4 0 0 0 0 D3 0 0 0 0 D2 0 0 0 0 D1 0 0 1 1 LAST LSB D0 0 1 0 1 1 1 1 Don't care. DAC output (VrefU-VrefL)/256 x 1+VrefL (VrefU-VrefL)/256 x 2+VrefL (VrefU-VrefL)/256 x 3+VrefL (VrefU-VrefL)/256 x 4+VrefL 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 (VrefU-VrefL)/256 x 255+VrefL VrefU MITSUBISHI ELECTRIC ( 5 /5) |
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